This application claims the priority of Korean Patent Application No. 2003-60766 filed on Sep. 1, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of Invention
The present invention relates to an integrated semiconductor device and a method of fabricating the same, and more particularly, to a system-on-chip containing a DRAM and an analog device, and a method of fabricating such a system-on-chip.
2. Background of the Invention
Advances in semiconductor manufacturing techniques have lead to a considerable reduction in the size of electronic products. This has made possible the development of products called “systems on chip” (SOC) products. SOCs are chips that perform multiple functions. SOCs have been developed for products in various fields. Moreover, a new SOC containing a DRAM and an analog device has been introduced.
An SOC containing a DRAM and an analog device generally includes a capacitor used as a unit cell for a DRAM. The capacitor should have a surface that is large enough to ensure a high capacitance. However, due to the requirement of high integration, it is necessary to form a capacitor having a high capacitance in a narrow space. Decreasing the size of the capacitor allows a reduction in the size of the analog device, thereby increasing the overall degree of integration.
Several attempts have been made to increase the density of capacitors in SOCs containing a DRAM and an analog device. In general, there are three methods of increasing the capacitance of a semiconductor capacitor based on the fact that, in general, the capacitance of a semiconductor capacitor is directly proportional to the surface of electrode and the dielectric constant of the dielectric layer, and inversely proportional to the thickness of the dielectric layer.
The first method involves increasing the contact surface between the electrode and the dielectric layer of the capacitor. That is, the capacitance is increased by designing an upper electrode and a lower electrode of the capacitor in a three-dimensional configuration. However, this method has a drawback in that making the capacitor in a three-dimensional configuration requires a relatively complicated manufacturing process.
The second method involves making a capacitor with a thin dielectric layer. Since the capacitance is inversely proportional to the thickness of the dielectric layer, the capacitance can be increased by decreasing the thickness of the dielectric layer. However, there is a limit to how much the thickness of the dielectric layer can be decreased owing to the characteristics of the dielectric layer itself.
The third method involves adopting a material with a high dielectric constant for the dielectric layer. However, this method also has many disadvantages. For example it may be difficult to adapt a new dielectric material to an existing process. Furthermore it may require a new electrode material and to it is necessary to verify the reliability of the new electrode material.